1. Technical Field
The present invention relates to semiconductor memory devices and more particularly, to a semiconductor memory device controlling a program voltage according to the number of memory cells to be programmed and a method of programming the same.
2. Discussion of the Related Art
Semiconductor memory devices are storage units capable of retaining data that may be read out as needed. Semiconductor memory devices may either be volatile memory devices that lose data in the absence of power or nonvolatile memory devices that retain data even without power. Flash memory is an example of a non-volatile memory.
Flash memory may either be NAND type or NOR type. NOR flash memory is often used for code storage. For example, NOR flash memory is used in mobile telephone terminals because NOR flash memory provides fast data processing and is operable at high frequencies. NAND flash memory conducts programming and erasing operations by means of Fowler-Nordheim (F-N) tunneling. In NOR flash memory, programming operations are carried out by hot electron injection and erasing operations are carried out by F-N tunneling. NOR flash memory is differentiated into stack-gate and split-gate types in accordance with the gate structure of the memory cells.
FIG. 1 is a sectional diagram showing a stack-gate memory cell 10 of a NOR flash memory. Referring to FIG. 1, the memory cell 10 is constructed of N+ source and drain regions 13 and 14, respectively, which are formed in a P-type substrate 19. A floating gate (FG) 16 is formed over a channel region through an isolation film 15 having a thickness of less than 100 Å. A control gate (CG) 18 is formed over the floating gate 16 through an intergate insulation film, for example, an oxide-nitride-oxide (ONO) film 17. The source region 13, the drain region 14, and the control gate 18 are coupled to a source line SL, a bit line BL, and a word line WL, respectively.
During a programming operation, the source line SL and the substrate 19 are grounded. The word line WL is supplied with a word line voltage of approximately 10V and the bit line BL is supplied with a bit line voltage of approximately 5V. Under such a bias condition, electrons are injected into the floating gate 16 from the channel region adjacent to the drain region 14. This mechanism is referred to as hot electron injection, which is a feature of the NOR flash memory.
Generally, during the programming operation, when a voltage of approximately 5V is applied to the drain region 14 of the memory cell, a cell current of approximately 200 μA flows from the drain region 14 toward the source region 13 through the channel region. For example, in programming multiple bits of data, for example, bytes or words of data, at the same time, the cell current is at most approximately 1.6 mA (200 μA×8) for a byte or 3.2 mA (200 μA×16) for a word.
FIG. 2 is a sectional diagram showing a split-gate memory cell 20 of a NOR flash memory. Referring to FIG. 2, the memory cell 20 is constructed of N+ source and drain regions 23 and 24, respectively, which are formed in a P-type substrate 29. A floating gate (FG) 26 is formed over a channel region through a gate oxide film 25. A control gate (CG) 28 is formed over the floating gate 26. The gate oxide film 25 is formed through a tunnel oxide film 27. The source region 23, the drain region 24, and the control gate 28 are coupled to a source line SL, a bit line BL, and a word line WL, respectively.
Examples of bias voltages applied to the memory cell 20 for a programming operation are described herein. A source line voltage VSL of approximately 9V is applied to the source line SL. A word line voltage VWL of approximately 2V is applied to the word line WL. The bit line BL is supplied with a bit line voltage VBL of approximately 0.5V or approximately 2V in accordance with program data. Under this bias condition, electrons are injected into the floating gate 26 from the channel region adjacent to the source region 23 by hot electron injection.
In the NOR flash memory device with split-gate structure, during the programming operation, a program voltage of approximately 9V is applied to the source line SL. This program voltage is supplied from a program voltage generator that is included in the NOR flash memory device. The program voltage generator includes a regulator fbr generating a program voltage of a constant level. The program voltage output from the program voltage generator drops while passing through a driver and a source line selection circuit. For example, the source line voltage VSL is applied to the source line SL at a voltage lower than the program voltage output from the program voltage generator.
The drop of the source line voltage VSL becomes more problematic as the number of memory cells to be programmed at a time increases. For example, 32 memory cells may be programmed at the same time. The 32 memory cells include cells to be programmed (hereinafter, referred to as ‘program cells’) and cells to be inhibited in programming (hereinafter, referred to as ‘program-inhibit cells’). The program cells are memory cells that are changed from an erased state to a programmed state. The program-inhibit cells are memory cells that remain in an erased state.
In the above example, the voltage drop of the source line voltage VSL is different when the number of program cells is 1 than when the number of program cells is 32. As the number of program cells increases, the source line voltage VSL becomes lower. The dropping pattern of the source line voltage VSL according to the number of program cells is shown in FIG. 6A. Such a drop of the source line voltage VSL according to the number of program cells would degrade program characteristics of the memory cells. For example, the number of program cells may affect a degree of stress that is placed upon the memory cells. Further, a large number of program cells can cause program failures due to insufficient cell currents.